A semiconductor chip, also commonly referred to as an integrated circuit (IC) chip or a die is typically assembled into a semiconductor chip package that is soldered to a printed circuit board. One type of semiconductor chip package is a flip chip, also known as a C4 package. The semiconductor chip package typically includes the IC chip, which contains a number of round solder bumps that are attached to a top surface of the chip. The IC chip, via the solder bumps, is soldered to solder pads located along a surface of a package substrate, forming a metallurgical joint between the chip and the substrate referred to as a C4. C4s carry electrical current between the semiconductor chip and the substrate.
The final metallurgical composition of a C4 is the combined result of the volumes and compositions of the solder bump on the IC chip and the solder pads on the package substrate. As the pitch is reduced, the solder bump dimensions on the IC chip are reduced. The package substrate solder pads typically account for about one third of the total solder volume of the final C4; the other two thirds comes from the solder bumps on the IC chip itself. For finer and finer pitch, such as required by 14 nm technology and beyond, the volume balance tends to shift from about a 2:1 ratio to about a 1:1 ratio of solder on the IC chip to solder on the package side. Thus, at fine pitches, it becomes advantageous to control package side solder volume in order to satisfactorily control the metallurgical composition of the final C4. The size reduction of the solder pads on the package substrate is limited, however, by the manufacturing constraints of the package manufacturing processes, which are coarser than manufacturing processes on the IC chip side.
Another factor in chip packing fabrication is the coefficient of thermal expansion (CTE) of the package substrate and the IC chip. The package substrate is typically constructed from a composite material which has a higher CTE than the CTE for the semiconductor chip. As a result, the IC chip expands relatively slowly in comparison to the package substrate, which expands relatively quickly under heat during chip join processes.
One method of compensating for the differences in CTE has been to compensate for the differing CTEs with adjusted solder volumes on the package side. In this process, the locations and volume of package solder pads are adjusted to improve chip join yields. Since the solder composition on the package side is typically standardized, compensating for differences in CTE with package side solder adjustments produces the undesirable effect of increasing the variability in solder volume in the resulting C4, and therefore the final metallurgical composition of the C4. This has implications for the strength and stiffness of the chip joint, among other attributes.